Characterization And Optimization Of Avalanche Photodiodes Fabricated By Standard Cmos Process For High-Speed High-Speed Photoreceivers

A dissertation presented on the characterization and optimization of avalanche photodiodes fabricated by standard CMOS process (CMOS-APD) for high-speed photoreceivers, beginning with the theory and principle related to photodetector and avalanche photodiodes, followed by characterization,optimization, and wavelength dependence of CMOS-APD, and finally link up with the transimpedance amplifier. nMOS-type and pMOS-type silicon avalanche photodiodes were fabricated by standard 0.18 μm CMOS process, and the currentvoltage characteristic and the frequency response of the CMOS-APDs with and without the guard ring structure were measured. CMOS-APDs have features of high avalanche gain below 10 V, wide bandwidth over 5 GHz, and easy integration with electronic circuits. In CMOS-APDs, guard ring structure is introduced for high-speed operation with the role of elimination the slow photo generated carriers in a deep layer and a substrate. The bandwidth of the CMOS-APD is enhanced with the guard ring structure at a sacrifice of the responsivity. Based on comparison of nMOS-type and pMOS-type APDs, the nMOS-type APD is more suitable for high-speed operation. The bandwidth is enhanced with decreasing the spacing of interdigital electrodes due to decreased carrier transit time and with decreasing the detection area and the PAD size for RF probing due to decreased device capacitance. Thus, an nMOS-type APD with the electrode spacing of 0.84 μm, the detection area of 10 x 10 μm², the PAD size for RF probing of 30 x 30 μm² along with the guard ring structure was fabricated. As a results, the maximum bandwidth of 8.4 GHz at the avalanche gain of about 10 and the gain-bandwidth product of 280 GHz were achieved. Furthermore, the wavelength dependence of the responsivity and the bandwidth of the CMOS-APDs with and without the guard ring structure also revealed. At a wavelength of 520 nm or less, there is no difference in the responsivity and the frequency response because all the illuminated light is absorbed in the p+-layer and the Nwell due to strong light absorption of Si. On the other hand, a part of the incident light is absorbed in the Psubstrate and the photo-generated carriers in the P-substrate are eliminated by the guard ring structure for the wavelength longer than 520 nm, and then bandwidth was remarkably enhanced at the sacrifice of the responsivity. In addition, to achieve high-speed photoreceivers, two types of TIA which are common-source and regulated-cascode TIAs were simulated by utilizing the output of the CMOSAPDs.The figure of merits of gain-bandwidth product was used to find the ideal results of the transimpedance gain and bandwidth performance due to trade-offs between both of them. The common-source TIA produced the transimpedance gain of 22.17 dBΩ, the bandwidth of 21.21 GHz and the gain-bandwidth product of 470.23 THz × dBΩ. Besides that, the simulated results of the regulated-cascade TIA configuration demonstrate 79.45 dBΩ transimpedance gain, 10.64 GHz bandwidth, and 845.35 THz × dBΩ gain-bandwidth product. Both of these TIA results meet the target of this research and further encouraging this successful CMOS-APDs to realize high-speed photoreceivers

Wavelength dependence of silicon avalanche photodiode fabricated by CMOS process

Avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have features of high avalanche gain below 10 V, wide bandwidth over 5 GHz, and easy integration with electronic circuits. In CMOS-APDs, guard ring structure is introduced for high-speed operation by canceling photo-generated carriers in the substrate at the sacrifice of the responsivity. We describe here wavelength dependence of the responsivity and the bandwidth of the CMOS-APDs with shorted and opened guard ring structure. © 2017 Elsevier LtdEmbargo Period 12 month

Integrated cmos rectifier for rf-powered wireless sensor network nodes

This article presents a review of the CMOS rectifier for radio frequency energy harvesting application. The on-chip rectifier converts the ambient low-power radio frequency signal coming to antenna to useable DC voltage that recharges energy to wireless sensor network (WSN) nodes and radiofrequency identification (RFID) tags, therefore the rectifier is the most important part of the radio frequency energy harvesting system. The impedance matching network maximizes power transfer from antenna to rectifier. The design and comparison between the simulation results of one- and multi-stage differential drive cross connected rectifier (DDCCR) at the operating frequencies of 2.44GHz, and 28GHz show the output voltage of the multi-stage rectifier doubles at each added stage and power conversion efficiency (PCE) of rectifier at 2.44GHz was higher than 28GHz. The (DDCCR) rectifier is the most efficient rectifier topology to date and is used widely for passive WSN nodes and RFID tags

Integrated CMOS rectifier for RF-powered wireless sensor network nodes

This article presents a review of the CMOS rectifier for radio frequency energy harvesting application. The on-chip rectifier converts the ambient low-power radio frequency signal coming to antenna to useable DC voltage that recharges energy to wireless sensor network (WSN) nodes and radiofrequency identification (RFID) tags, therefore the rectifier is the most important part of the radio frequency energy harvesting system. The impedance matching network maximizes power transfer from antenna to rectifier. The design and comparison between the simulation results of oneand multi-stage differential drive cross connected rectifier (DDCCR) at the operating frequencies of 2.44GHz, and 28GHz show the output voltage of the multi-stage rectifier doubles at each added stage and power conversion efficiency (PCE) of rectifier at 2.44GHz was higher than 28GHz. The (DDCCR) rectifier is the most efficient rectifier topology to date and is used widely for passive WSN nodes and RFID tag

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

nMOS-type and pMOS-type silicon avalanche photodiodes (APDs) were fabricated by standard 0.18µm CMOS process, and the current-voltage characteristic and the frequency response of the APDs with and without guard ring structure were measured. The role of the guard ring is cancellation of photo-generated carriers in a deep layer and a substrate. The bandwidth of the APD is enhanced with the guard ring structure at a sacrifice of the responsivity. Based on comparison of nMOS-type and pMOS-type APDs, the nMOS-type APD is more suitable for high-speed operation. The bandwidth is enhanced with decreasing the spacing of interdigital electrodes due to decreased carrier transit time and with decreasing the detection area and the PAD size for RF probing due to decreased device capacitance. The maximum bandwidth was achieved with the avalanche gain of about 10. Finally, we fabricated a nMOS-type APD with the electrode spacing of 0.84µm, the detection area of 10×10µm2, the PAD size for RF probing of 30×30µm2, and with the guard ring structure. The maximum bandwidth of 8.4GHz was achieved along with the gain-bandwidth product of 280GHz

A Pixel Matching Process And Multiples Roi For Stereo Images In Stereo Vision Application

This paper presents an analysis of stereo images for an application of stereo vision application. The matching process is to determine the difference of intensities of pixel between stereo images while the region of interest ROI works as a reference area to the stereo vision application. This region is a reference view of the stereo camera and stereo vision baseline is based on horizontal configuration. The block matching technique is briefly described with the performance of its output. The disparity mapping is generated by the algorithm with the reference to the left image coordinate. The algorithm uses Sum of Absolute Differences (SAD) which is developed using Matlab software. The rectification and block matching processes are also briefly described in this paper

An Investigation on I-V Characteristic for CMOS PIN Photodiode: Variable I-Layer

In this paper presented an investigation on I-V characteristic for CMOS PIN Photodiode. PIN diodes are widely used in optics and microwave circuits as it acts as a current controlled resistor at these frequencies. PIN diode performance is greatly influenced by the geometrical size of the device, especially in the intrinsic region. Two different I-layer thickness of PIN diode structure has been designed using Sentaurus Technology Computer Aided Design (TCAD) tools. The I-layer thickness (or width) is varied from 4 µm to 8 µm in order to investigate its effects on the current-voltage (I-V) characteristics. These structures were design based on CMOS process. Keyword - PIN Photodiode, Silvaco TCAD, IV Characteristic, Reverse Bias

Characterization Of SiO2/SiC Interface Of Phosphorous-Doped MOS Capacitors By Conductance Measurements

Interface states of MOS structures capacitors incorporated with low levels of phosphorous have been investigated by conductance and C-ψs method. The frequency response of interface states was observed by the conductance method up to 10 MHz. The correlation between the frequency response of interface states and interface state density determined by C-ψs method was studied. It was found that fast states in phosphorous incorporated samples reduced significantly at high frequency (>5 MHz) while sample annealed with nitrogen remained high up to 10 MHz. The interface state density, Dit of phosphorous incorporated sample near conduction band is lower compared to nitridated sample. These results indicate phosphorous passivation effectively reduces Dit at the SiO2/SiC interfaces and can be correlated to high channel mobility

Design Consideration And Impact Of Gate Length Variation On Junctionless Strained Double Gate MOSFET

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (Lg) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (Lg) does contributes a significant impact on the drain current (ID), on-current (ION), off-current (IOFF), ION/IOFF ratio, subthreshold swing (SS) and transconductance (gm). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both ION and gm(max) are measured at 1680 µA/µm and 2.79 mS/µm respectively

UWB Antenna Width Tuning Effect for UWB Communication

In this paper, a performance analysis of an array of 2 x 1 Ice Cream Cone UWB Antenna for Ultra Wide Band (UWB) communication is being proposed. The antenna designs have been simulated using CST Microwave Studio. The antenna covers the UWB spectrum from 3.1 to 10.6 GHz, and had a return loss below than -10 dB throughout the entire band. The basic antenna analysis has been done including the analysis of antenna performance due to antenna width tuning. A compact antenna area of 70 x 80 mm2 is obtained. The material used is FR-4 epoxy glass substrate that has dielectric constant, r = 4.4 and the dielectric thickness; h = 1.6mm. The antenna also gives omni-directional radiation characteristics with reasonable gain values over the same frequency ban